| 产品规格︰ | 15 ms maximum average periodic refresh interval
Auto Precharge option
Available in 128/256/512 MB module package
4 internal banks for concurrent operation
Programmable burst lengths:2,4 or 8
Differential clock inputs (CKO and CKO#)
Bidirectional data strobe (DQS) transmitted/received with data i.e., source-synchronous data capture
Auto Refresh (CBR) and Self Refresh
Internal, piplined double data rate (DDR) architechture; 2 data accesses per clock cycle
DQS edge-aligned with data for READs; center-aligned with data for WRTIEs
2.5V I/O (SSTL-2 compatible)
VDD=+2.5V 0.2V, VDDQ= +2.5V+-0.2V
Commands entered on each positive CK edge
184-pin Dual in-line memory modules (DIMM)
TSOP66 Package
|
|
|
|
